Embodiments of the present invention relate to forming metal silicide on silicon-containing features of a substrate.
Low resistivity metal silicide regions are formed on semiconductor features to enable electrical interconnection of components of a semiconductor device. Self-aligned suicides (referred to as “salicides”) are formed on silicon-containing features, such as gates, to provide a layer of low resistivity material on the feature. In the self-aligned silicide processing method, a metal is deposited on the features and then reacted with portions of the features exposed to the metal to form silicide regions on the exposed portions. Portions of the features that are not exposed, e.g., portions covered by a spacer, do not form a silicide region. In this manner, self-aligned silicides are selectively formed on the features without patterning or etching deposited silicide to define low resistively regions. Self-aligned suicides can be formed from metals that include nickel, titanium, cobalt, and other metals that can react with silicon materials to form silicides.
A conventional method of fabricating a self-aligned silicide structure known as a one-step rapid thermal anneal (RTA) process, is shown in FIGS. 1A-1C. FIG. 1A shows a silicon substrate 10 having silicon-containing features 16 that can be, for example, polycrystalline silicon. i.e., polysilicon, gate structures. The features 16 have adjacent spacers 14 that are typically a silicon oxide, silicon nitride, or other such ceramic material. The silicon substrate 10 has active regions 12 comprising doped silicon, that serve as a source and a drain of a transistor. In FIG. 1B, a layer of a silicide-forming metal or metal alloy 18 is deposited over the silicon-containing features 16. The multilayer structure of FIG. 1B then undergoes a rapid thermal anneal (RTA) process step at temperatures exceeding 500° C., causing the metal layer 18 to react with the exposed regions of the silicon-containing features 16. FIG. 1C shows the substrate 10 after the high temperature anneal step, where low resistivity metal silicide 20, 22 is formed over the active regions 12 and over the features 16, respectively.
Another conventional process, known as a two-step RTA process, is shown in FIGS. 2A-2D. FIG. 2A shows the silicon substrate 10 having silicon-containing features 16 that have adjacent spacers 14. In FIG. 2B, the silicide-forming metal or metal alloy 18′ is deposited at room temperature on the silicon-containing features 16, and then a first low temperature annealing process is conducted at temperatures of less than about 300° C. to form a high resistivity metal silicide layer 20′, 22′ over the active regions 12 and over the features 16, respectively (FIG. 2C). Unreacted metal on the silicon-containing features 16 or other dielectric layer is removed by wet etch. Then a second higher temperature annealing process is conducted at temperatures exceeding 450° C. to form the low resistivity metal silicide layer 24, 26 over the active regions 12 and over the features 16, respectively (FIG. 2D).
As semiconductor technology advances, it has become desirable for the dimensions of certain semiconductor features to become smaller. For example, it is desirable for a polycrystalline region and spacers to be formed as small as possible on a semiconductor substrate to enhance performance of semiconductor devices using this type of feature. For example, transistors adopting this general semiconductor feature are designed and implemented with such small dimensions to enable the transistor to execute computer instructions at faster speeds. The above described processes for forming a low resistivity metal silicide are not suitable for such small features.
For example, the one-step RTA process is particularly troublesome for certain silicide-forming metals, such as nickel. It has been observed that at the rapid thermal anneal temperatures ranging from 350° C. to 700° C. the reaction rate between the nickel and silicon is difficult to control resulting in the excessive formation of nickel silicide 20″, 22″ on the active regions 12 and features 16 that can lead to undesirable bridging. (FIG. 3.) Moreover, as is shown in FIG. 4, it has been observed that small (or short) features 16b tend to convert entirely or nearly entirely into nickel silicide 22b while larger (or taller) features 16a are partially converted. Conversion of the entire feature 16b to the metal silicide 22b is undesirable but inevitable given the difference in size between the larger feature 16a and the smaller feature 16b and given the uncontrollable reaction rates at the high anneal temperatures.
Moreover, particular metals present certain challenges. For example, the use of titanium in the two step RTA process to form titanium silicide in a self-aligned manner is not effective with semiconductor structures of smaller dimensions because titanium metal or titanium alloy does not fully react with the small surfaces of silicon materials such as the polycrystalline silicon region 16 and active regions 12 of FIG. 5. As is shown, the reaction mechanism between titanium and silicon is by nucleation, and therefore clusters 24′, 26′ of titanium silicide form. The clusters 24′, 26′ are scattered, and inconsistent, and do not adequately lower the resistivity of the silicon based components of the semiconductor structure. Hence, the use of titanium does not adequately serve the objectives of forming silicides in a self-aligned manner for relatively small semiconductor structures.
Cobalt can also be reacted with silicon containing features 16 to form self-aligned cobalt silicide regions in a semiconductor structure utilizing the two-step RTA process. Nevertheless, the temperatures at which the first and second RTAs are conducted are relatively high. For example, for cobalt, the first RTA is at temperatures ranging from 450° C. to 510° C. and the second RTA is at temperatures ranging from 760° C. to 840° C. These high temperatures can induce stress on the semiconductor structure and can destroy the functionality of the semiconductor device and limit the designs of the semiconductor structures utilizing self-aligned suicides. In addition, these relatively high temperatures may not be compatible or desirable with semiconductor processing of pre-existing components of the semiconductor structure. More particularly, these high temperatures may diffuse materials of the existing semiconductor structure.
A nickel silicide layer can also be formed utilizing the two-step RTA process, where a metal film comprising nickel is deposited at room temperature, the first RTA is at approximately 300° C. and the second RTA is at approximately 450° C. after wet etch of unreacted nickel. Nevertheless, the resultant nickel silicide layer exhibits poor thermal stability at high temperatures. e.g., ranging from about 700° C. to 800° C., due to agglomeration and/or NiSi2 formation. Thus, such a nickel silicide layer becomes ineffective as a low resistivity layer eventually causing device failure.
Moreover, the one-step and two-step RTA processes are time-consuming and generally performed in at least two different chambers: one for depositing the metal film and another for performing the anneal(s). This increases the chances of contamination of the substrates during the transportation from one chamber to another the two-step RTA process is also slower and increases processing costs.
Accordingly, it is desirable to control the formation rate of the silicide to reduce silicide formation in and around the features. It is also desirable to form metal silicide regions that are thermally stable at high processing temperatures. It is further desirable to have a metal silicide process that can be performed in a single process chamber.